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ST70136
CPE ADSL ANALOG FRONT END
s WIDE TRANSMIT AND RECEIVE DYNAMIC s s s s s s s s s s s s
RANGE TO REDUCE EXTERNAL FILTERING REQUIREMENTS RECEIVE PROGRAMMABLE GAIN: 0 TO 31dB GAIN IN 1dB STEPS RECEIVE PROGRAMMABLE ATTENUATOR 0,-4dB, -8dB, -12dB 12-BIT A/D CONVERTER IN RECEIVE PATH TRANSMIT PROGRAMMABLE GAIN: 0 TO -15dB IN 1dB STEPS 14-BIT D/A CONVERTER IN TRANSMIT PATH LOW POWER MODE: 10mW IN LISTENING MODE, 250W IN POWER DOWN TONE DETECTOR: ACTIVITY DETECTION FOR WAKE-UP FUNCTION 64-PIN TQFP PACKAGE 64-PIN LFBGA PACKAGE 0.50m, 5V BICMOS TECHNOLOGY 3.3V DIGITAL INTERFACE 5V ANALOG INTERFACE The AFE receive path contains a programmable gain amplifier (RxPGA), a low pass anti-aliasing filter, and a 12-bit A/D converter. The RxPGA is digitally programmable from 0 to 31dB in 1dB steps. The AFE transmit path consists of a 14-bit D/A converter, followed by a programmable gain amplifier (TxPGA). The transmit gain is programmable from 0 to -15dB in 1dB steps.
TQFP64 Full Plastic (10 x 10 x 1.40 mm) ORDER CODE: ST70136G
INTRODUCTION The ST70136 ADSL Analog Front End (AFE) chip implements the analog transceiver functions required in a Customer Premise ADSL modem. It connects the digital modem chip with the loop driver and hybrid balance circuits. The AFE has been designed with high dynamic range in order to greatly reduce the external filtering requirements at the front end. The AFE chip and its companion digital chip along with a loop driver, implement the complete G.992.2 and G.992.1 DMT modem solution. Figure 1 : Overall Application Block Diagram
Software for Control xDSL
LFBGA64 (8 x 8 x 1.7 mm) ORDER CODE: ST70136B
PC
PCI or USB
PCI or USB
LINE DMT xDSL AFE LOOP DRIVER HYBRID
ST70137
ST70136
TS612/TS652
September 2001
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ST70136
ST70136 Pinout
VDDOSC
VCOCAP
VCXOUT
VSSOSC VSSESD
VDDA6
VDDA5 50 48 VSDA VDDA4 PGAP TXIN TXP TXN TXIP PGAN VSSA4 VSSA3 V290DA V125AD V250AD 35 34 33 V375AD VSBIAS V3P75V 47 46 45 44 43 42 41 49 VSSA5 40 39 38 37 36 32 IREF50U 31 VDDA3
XTALO
VSSA6
XTALI
IVCO
TON
TOP
GC0 52 51 29 RXN 30 VDDA1
64 CTRLIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 SUSPEND VDDA2 VSSA2 VSAD VDD PWD NRESET VSSA1 TEST VSRX RXP VSS 18 19 20 21 22 23 24 25 26 27 28 CTRLOUT R/W VDDIO CLKWD CLKM ACTD RX3 RX2 RX1 RX0 VSSIO TX3 TX2 TX1 TX0
63
62
61 60
59 58
57
56
55
54
53
ST70136G
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GC1
ST70136
1 - PIN LIST The following list gives the different PIN Types: AI Analog Input AIO Analog Input/Output AO Analog Ouptut DI Digital Input DIO Digital Input/Output Table 1 : Pin Assignment
Pins Name TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 LFBGA B2 C3 C2 B1 A1 C1 D2 D1 E2 E1 F2 G2 F1 G1 H2 H1 E3 G3 E4 H3 F3 G4 F4 H4 G5 E5 H5 H6 CTRLIN CTRLOUT R/NW* VDDIO CLKWD CLKM ACTD RX3 RX2 RX1 RX0 VSSIO TX3 TX2 TX1 TX0 VSS TEST NRESET* VDD PWD SUSPEND VDDA2 VSSA2 VSAD VSRX VSSA1 RXP DI DO DI VDDD DO DO O DO DO DO DO VDDD DI DI DI DI VSSD DI DI VSSD DI DI VDDA VSSA VSSA VSSA VSSA AI Digital input for control interface Digital output for control interface Selection of read or write mode for control interface I/O buffer supply voltage 8.832MHz output clock. Used to synchronize RX/TX word data exchange, and master clock of register control interface 35.328MHz Master Clock. Xtal buffer Tone Detector Activation Received data output Received data output Received data output Received data output I/O buffer ground voltage Transmit data input Transmit data input Transmit data input Transmit data input Core digital ground Test mode is activated with TEST=1. Must be tied to ground in normal mode Reset input. All digital circuitry is well defined after a negative pulse on this input Core digital supply (3.3V) Power Down pin Suspend Mode pin ADC supply voltage (5V) ADC ground voltage Substrate voltage for RX-AD path (Must be connected to VSSAx) Substrate voltage for RXPGA path (Must be connected to VSSAx) RXPGA ground voltage Positive Analog Receive input Type Description
DO VDDA VDDD VSSA VSSD
Digital Output Analog Power Supply Digital Power Supply Analog Ground Digital Ground
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Table 1 : Pin Assignment (continued)
Pins Name TQFP 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 LFBGA H7 G6 F5 H8 G8 G7 F7 F8 F6 E7 E8 E6 D6 D8 D7 C7 C8 B7 B8 A8 A7 C6 A6 B6 D5 C5 B5 D4 A5 C4 A4 B4 D3 A3 B3 A2 RXN VDDA1 VDDA3 IREF50U V3P75V VSBIAS V375AD V250AD V125AD V290DA VSSA3 VSSA4 PGAN TXIP TXN TXP TXIN PGAP VDDA4 VSDA VSSA5 VDDA5 GC1 GC0 VDDA6 TON TOP VCXOUT IVCO VCOCAP VSSA6 VSSESD VSSOSC XTALI XTALO VDDOSC AI VDDA VDDA AI AO VSSA AO AO AO AO VSSA VSSA AO AI AO AO AI AO VDDA VSSA VSSA VDDA DO DO VDDA AI AI AIO AIO AO VSSA VSSD VSSD DI DO VDDD Negative Analog Receive input RXPGA voltage supply (5v) Bias and References voltage supply (5v) External resistor for bias current 50k 3.75v output from bandgap; 0.22F decoupling Substrate voltage for biasing & reference cell (Must be connected to VSSAx) 3.75 volt reference voltage. Need decoupling 0.1F 2.50 volt reference voltage. Need decoupling 0.1F 1.25 volt reference voltage. Need decoupling 0.1F 2.90 volt reference voltage. Need decoupling 0.1F Biasing and References ground voltage Tx path ground voltage Negative TXPGA output Positive analog input for Tx external filtering Negative analog transmit output Positive analog transmit output Negative analog input for Tx external filtering Positive TXPGA output Tx analog supply voltage (5V) Substrate voltage for DAC path (Must be connected to VSSAx) DAC path ground voltage DAC analog supply voltage (5v) MSB for external gain control LSB for external gain control VCXO & Tone detector Input analog supply voltage (5v) Negative tone detector input Positive tone detector input VCXO output current VCXO input current VCXO output filtering VCXO & Tone detector analog ground voltage Ground voltage reference for ESD Ground voltage for Xtal oscillator Xtal oscillator input Xtal oscillator output Supply voltage for Xtal cell (3.3v) Type Description
* A "N" means active low. Example: R/NW means write active low.
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2 - PIN DESCRIPTION 2.1 - Analog Power Supplies These pins are the positive analog power supply voltage for the DAC and the ADC section. It is not internally connected to digital supply. In any case the voltage on these pins must be higher or equal to the voltage of the Digital power supply. 2.2 - Digital Power Supplies These pins are the power supply pins that are used by the internal digital circuitry. All DVDD pins must be connected together to a +3.3 V supply. 2.3 - Analog Ground and Substrate These pins are the ground return of the analog DAC and ADC blocks. The analog VDDA should be decoupled with respect to the analog ground. Decoupling capacitors should be as close as possible to the supplies pins. All grounds must be tied together. 2.4 - Digital Ground These pins are the ground return of the digital circuitry. The digital power supplies must should be decoupled with respect to the digital ground. Decoupling capacitors should be as close as possible to the supplies pins. All grounds must be tied together. 2.5 - Powerdown - PWD When pin PWD ="1", the chip is set in low power mode. 2.6 - Suspend The SUSPEND pin is used to control the output of CLKM. When SUSPEND is low CLKM output is enabled otherwise CLKM is disabled. 2.7 - Reset The reset function is implied when the NRESET pin is at a low voltage input level. In this condition, the reset function can be easily used for power up reset conditions. Reset is asynchronous, tenths of ns are enough to put the IC in reset. After reset, all registers are set to their default value. 2.8 - Reference Voltages 2.8.1 - V125AD, V250AD, V375AD These pins are used to externally decouple the internal reference voltages used for the ADC (1.25V, 2.5V, 3.75V). 2.8.2 - V3P75V This pin is the 3.75V Bandgap output and should be externally decoupled with an external capacitor of 0.22uF. 2.8.3 - IREF50U This pin is used for setting the bias current and must be externally connected to a resistor of 2.5V / 50A equals 50k. 2.8.4 - V290DA This pin is the 2.9V transmit DAC output reference voltage and must be decoupled externally. 2.9 - Analog Transmit Output 2.9.1 - TXP This pin is the non-inverting output of the fully differential analog amplifier. 2.9.2 - TXN This pin is the inverting output of the fully differential analog amplifier. 2.9.3 - TXIP This pin is the differential non-inverting input for external filtering. 2.9.4 - TXIN This pin is the differential inverting input for external filtering. 2.9.5 - PGAP This pin is the differential non-inverting PGA output. 2.9.6 - PGAN This pin is the differential inverting PGA output. 2.10 - Analog Receive Input 2.10.1 - RXN This pin is the differential inverting receive input. 2.10.2 - RXP This pin is the differential non-inverting receive input. 2.11 - Tone Detector The analog input differential signal must be less than 8V peak to peak. These pins are used for activity detection when in sleeping mode. 2.11.1 - TON This pin is the differential inverting tone detector input.
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2.11.2 - TOP This pin is the differential non-inverting tone detector input. 2.11.3 - ACTD This pin is active when tone 40 or 72 has been detected in sleeping mode (see control register) 2.12 - CRYSTAL These pins must be tied to an external crystal (F = 35.328MHz). 2.12.1 - XTALI This pin is the crystal oscillator input. 2.12.2 - XTALO This pin is the crystal oscillator output. 2.13 - VCXO 2.13.1 - IVCO This pin is the current reference for the VCO DAC 2.13.2 - VCOCAP This pin is used to introduce time constant. The tuning is done by connecting an external capacitor 2.13.3 - VCXOUT This pin is the output control current generated by a 8 bit DAC. 2.14 - Control Serial Interface Access to the control register can be done only in stable state fonctionality: SUSPEND = "0". 2.14.1 - CTRLIN This pin is used to program the internal registers. The data burst is composed of 16 bits sampled at CLKM when CLKWD = 1. The first bit is used as start bit ('0'), the three LSBs being used to identify the data contained in the twelve remaining bits. The start bit b15 (b5 = 0) is transmitted first followed by bits b[14:0]. At least 1 stop bit "1" need to be provided to validate the data. 2.14.2 - CTRLOUT This pin is the control register output. The burst data on this pin is the value of the register addressed by CTRLIN. 2.14.3 - CLKWD This pin is the word clock used to sample the control information and equal to CLKM / 4. 2.14.4 - R/NW This pin is used for the read and write operation for the control interface and sampled at the same time than bit b15 of CTRLIN. 2.14.5 - Digital Interface The interface is a nibble serial interface running at 8.832MHz sampling frequency. The data are presented in 16bits format, and transferred in groups of 4 bits (nibbles). The LSBs are transferred first. Data is transmitted on the rising edge of the master clock CLKM 2.14.6 - CLKM This pin is the master clock equal to 35.328MHz and is the sampling clock of the input / output data. 2.14.7 - TX0, TX1, TX2, TX3 These pins are the digital transmit data input. 2.14.8 - RX0, RX1, RX2, RX3 These pins are the digital receive data output. 2.15 - Test This pin is dedicated to put the ST70136 in test mode.
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3 - BLOCK DIAGRAM
XTALI
XTALO
TEST
SUSPEND
PWD
V125AD V250AD V375AD V290DA V3P75V IREF50U
62
63
18
22
21
37
36
35
38
33
32
INTERNAL VCXO
POWER MANAGEMENT
BANDGAP REFERENCE
CLOCK GENERATOR 1 1 1 1 DATA INTERFACE 16 14-BIT DAC
42 TXIP
+ -
PA
43 TXN 44 TXP 45 TXIN 41 PGAN 46 PGAP
TX0 TX1 TX2 TX3 CLKM RX0 RX1 RX2 RX3 CLKWD ACTD CTRLIN CTRLOUT R/NW NRESET
16 15 14 13 6 11 10 9 8 5 7 1 2 3 19
+
TxPGA
1 1
16 1 1
12-BIT ADC
29 RXN
AAF RxPGA ATT
28 RXP
TONE DETECTOR
54 TON 55 TOP 52 GC0 51 GC1
CONTROL INTERFACE
8
8-BIT DAC
56 VCXOUT
58
VCOCAP
57
IVCO
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ST70136
4 - FUNCTIONAL DESCRIPTION 4.1 - General The ST70136 consists of the following functional blocks: - Transmit Signal Path - Receive Signal Path - Bias Voltage and Current Generation - Digital Data Interface - Control Serial Interface - Tone Detector - Power Down mode management 4.2 - Transmit Path Description The transmit path contains the 14-bit digital to analog converter (DAC) necessary to generate the transmit signal from a 16-bit digital input word. This transmit signal is then scaled by the on chip programmable gain amplifier (TxPGA) from 0 to -15dB in 1dB steps. The scaled output signal is then driven off chip to the external filters and power amplifier (PA) which drives the DMT signal to the subscriber loop. The transmit path is fully differential. 4.3 - Receive Path Description The receive path contains first an attenuator (which allows the selection between 4 attenuated versions of the signal) followed by a programmable gain amplifier (RxPGA), a 1st order low pass anti-aliasing filter, and a 12-bit analog to digital converter (ADC). The RxPGA gain is digitally programmable from 0 to 31dB in 1dB steps. The receive path is fully differential. 4.4 - VCXO The ST70136 contains the circuits required to construct an internal VCXO. It is divided in a crystal driver and an auxiliary 8 bits DAC for timing recovery. The crystal driver is able to operate at 35.328MHz. The DAC which is driven by the CTRLIN pin (the input of the Serial Control Interface), provides a current output with 8 bits resolution and can be used to tune the crystal frequency with the help of external components. A time constant between DAC input and VCXOUT can be introduced (via CTRLIN interface) and programmed with the help of an external capacitor (on VCOCAP pin). 4.5 - Bias Voltage and Current Generation The bias circuitry contains a bandgap voltage reference from which the converters references and analog ground voltages are generated. This block also generates an accurate bias current using an external resistor. 4.6 - Digital Data Interface To facilitate data transfer between the ST70136 and the digital data pump, a 4-bit wide serial interface for the transmit and receive path is incorporated into the AFE. This interface consists of four transmit pins (TX[0:3]), four receive pins (RX[0:3]), and the necessary control signals (CLKM, CLKWD) to transmit and receive the required data.
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ST70136
Figure 2 : Digital Data Interface
CLKM 35.328MHz CLKWD 8.832MHz TX[0]/RX[0] TX[1]/RX[1] TX[2]/RX[2] TX[3]/RX[3] a0 a1 a2 a3 a15 TX DATA Sign a4 a5 a6 a7 a8 a9 a10 a11 a14 a12 a13 a14 a15 a13 a0
DATA..................................................................................LSB
a15 RX DATA Sign
a14
a13
a2 a1 a0 00
Sign DATA.................................................................... 0
4.7 - Control Serial Interface There is a 4-pin serial digital interface (CLKWD, CTRLIN, CTRLOUT, R/W) that access one of the 8 x 12-bit registers that controls all the programmable features on the ST70136. The registers are loaded with the asynchronous type data burst delivered to CTRLIN pin. It is comFigure 3 : Control Register Interface Write Cycle
CLKM
posed of 16 bits from which the first bit (b15) is used as start bit (`0'), the three LSBs (b2:b0) being used to identify the register to be loaded. The twelve remaining bits (b14:b3) are the control data. During a read operation, the CTRLOUT pin figures out the register contents addressed by CTRLIN pin.
CLKWD
b15 CTRLIN
Data for write access [b14:b3]
[b2:b0]
CTRLOUT
R/NW
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ST70136
Figure 4 : Control Register Interface Read cycle
CLKM
CLKWD b15 CTRLIN b15 CTRLOUT R/NW Data [b14:b3] Don't care [b2:b0]
4.7.1 - AFE registers 4.7.1.1 - Rx Gain Control This register is located at the address "000" and is used to program the gain in the receive path. Table 2 : Rx Gain Control (address [b2:b0]="000")
Name GC[1:0] Pos. 14.13 Type R/W Def. 00 GC1 bit13: selects External Gain control GC0 Other RxAGC 12 11..7 R/W R/W 0 00000 Reserved Select internal gain for Receive amplifier 00000 : 0dB 11111 : 31dB RxAtt 6..5 R/W 00 Receive attenuator 00 = 0dB 01 = -4dB 10 = -8dB 11 = -12dB Other 4.3 R/W 00 Reserved Description bit14: selects External Gain Control
4.7.1.2 - Tx Gain Control This register is located at the address "001" and is used to program the gain in the transmit path. Table 3 : Tx Gain Control (address [b2:b0]="001")
Name TxAGC Pos. 14..11 Type R/W Def. 0000 Description Select internal gain for Transmit amplifier 0000 : -15dB 1111 : 0dB Other 10..3 R/W 0..0 Reserved
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4.7.1.3 - Special Features Configuration This register is located at the address "010" and is used to configure different blocks. Table 4 : Adsl Configuration (address [b2:b0]="010")
Name Reserved VCO-DAC Pos. 14.13 12 Type R/W R/W Def. 00 1 Reserved Enable the VCO DAC 1: enabled 0: disabled Other FVCXO 11.4 3 R/W R/W 0..0 0 Reserved Filtered VCXO output 1 : filtered 0 : not filtered Description
4.7.1.4 - VCXO Control Table 5 : VCXO DAC Value (address [b2:b0]="011")
Name DAC value pos. 14..7 type R/W def. 80H 8 bits for VCO DAC. 0...0 = min. current 1...1 = max current. Others 6..3 R/W 0000 Reserved Description
4.7.1.5 - Test Only Registers They are presently located at address "100" to "101". 4.7.1.6 - Tone Detection Threshold Setting Register Table 6 : Tone Detection Threshold Setting Register (address [b2:b0]="110")
Name Threshold Level Reserved Pos. 14..5 4.3 Type R/W R/W Def. 00 Reserved Description
1000000000 Set the threshold of the tone detector
4.7.1.7 - Status Register & tone detector This register can be used in the case of read / write registers. Table 7 : Status & Tone Detector Register (address [b2:b0]="111")
Name Receiver Clip indicator Transceiver Clip indicator Sleeping Mode Tone Detector Pos. 14 13 12 11 Type R/W_clear 1 R/W_clear R/W R/W Def. 0 0 0 0 Description 1: Receive Clipping occurred 1: Transmit Clipping occurred 0: disable tone detector in power down 1: enable tone detector in power down Tone detector frequency setting 0: standard ADSL (tone 40) 1: ADSL over ISDN (tone 72) Debug Mode 10 R/W 0 When in normal mode "0" the CTRLOUT pin is in HIZ and don't care for R/W and the control access register are always writing operation whatever on R/W pin. When in debug mode "1" the CTRLOUT and R/W pins are operating as defined in pin description chapter. Software Reset Reserved 9 8..3 R/W R/W 0 0..0 When set all registers are set to their default value Reserved
Note: 1. R/W_clear: bit is resetted to 0 by writing 0.
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4.8 - Tone Detector The tone detector is dedicated for remote activation. It operates during SUSPEND mode with PWD = 0 only. When the tone detector level received Vin over tone 40 or 72 is greater than 15V peak to peak, the ACTD pin is set to wake up the modem. ACTD pin is resetted when the AFE is back in full operating mode (SUSPEND = 0, PWD = 0). The maximum signal sensitivity at the Tone detector inputs is 50mV peak to peak. 4.9 - Mode Management 4.9.1 - General The ST70136 can be used in a various range of ATU-R equipments, but a specific mode management address USB application in its different modes. In following table, "CPE" is an USB ADSL modem application done with a ST70136 AFE and a ST70137 DMT. The CPE is connected to an USB port of an equipment. Table 8 : ST70136 / USB Operating Mode Configurations
SUSPEND 0 PWD 0 USB Mode Description Active mode The CPE application is in operative mode, its current consumption is less than 500 mA. ST70136 is power-up, the Tone detector is OFF and CLKM output is enabled. 0 1 Enumerating mode The CPE application is in the configuration process, plug in, its current consumption is less than 100 mA. ST70136 analog part is in power done mode, the digital part is enabled and CLKM output is enabled. 1 0 Suspend mode after enumerating mode After enumerating, the CPE application is in suspend mode, in this mode the CPE must be able to wake up the equipment when a tone is received, its current consumption is less than 2.5 mA. ST70136 analog and digital parts are in power down mode, the Tone detector is activated and CLKM output is disabled. 1 1 Stand by mode The CPE is not configured and in stand by mode, it could be wake up only by the equipment, its current consumption is less than 500A. ST70136 is fully in stand by mode and CLKM is disabled.
Figure 5 : USB Power Management Operating Modes
Plug in
Enumerating mode
PWD = 1 SUSPEND = 0
Suspend mode
PWD = 0 SUSPEND = 1
Stand by mode
PWD = 1 SUSPEND = 1
Active mode
PWD = 0 SUSPEND = 0
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4.9.2 - Reset Timing Figure 6 : Reset Timing
V
VDD t 7ms max
XTAL
5ms max Reset
5ms done by an external R/C network
Internal counter 2ms CLKM
CLKWD
SUSPEND After CLKM depends on SUSPEND, PWD pin status
4.9.3 - Mode Management Timing Figure 7 : Mode Management
Tone detector: Disabled 7ms max Enabled
XTAL
CLKM
SUSPEND
PWD
Stand by mode
Enumerating mode
Active mode
Suspend mode
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5 - SPECIFICATIONS 5.1 - Absolute Maximum Ratings Supply Voltage(AVDD,DVDD) Input Voltage Input current per pin Output current per pin Storage Temperature ESD Protection General DC Specification
Parameter AVDD DVDD - Active Analog Digital Oscillator - Listening Analog Digital Oscillator - Stand by Analog Digital Oscillator 10 10 5 11 25 25 10 1.1 0.6 11 1.7 1 75 10 2 85 30 5 mA mA mA A mA mA A A A Minimum 4.75 3 Typical 5 3.3 Maximum 5.25 3.6 Unit V V
-0.3V to 6V -0.3V to AVDD,DVDD + 0.3V -10mA to + 10mA -20mA to + 20mA -65C to 150C 2000V
5.2 - Characteristics for Digital Signals TA = 0 to 70C unless otherwise specified.
Parameter Iil Iih Ioz Vih Vil Voh Vol Col Low level input current High level input current Tri-state output leakage Input high voltage Input low voltage high level output voltage low level output voltage Output load capacitance Type DI DI DIO DI, DIO DI, DIO DO DO DO Ioh = 2mA Iol = 2mA 0.85 x VDD 20 Conditions Vi = 0v Vi = VDD Vo = 0v or VDD Minimum -1 -1 -1 0.8 x VDD 0.2 x VDD 0.4 Typical Maximum 1 1 1 Unit A A A V V V V pF
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ST70136
5.3 - Receive Path Specifications TA = 0 to 70C unless otherwise specified. The following specifications are guaranteed only when the Digital Control Interface is not active. Table 9 : Receive Path Specifications
Typical specifications apply for VCC = 5.0V, temperature = 27C, nominal process and bias current. Maximum and minimum performance is with VCC 5%, 0C < Tambient < 70C, and worst case process and bias current. Description Output word rate Output word resolution 16 bits Reference Input signal Common mode voltage Differential Input impedance Input noise Gain, 0 D 31 Step size 1dB
b a
Min.
Typ. 8.832
Max.
Unit MHz
Comments Data Sampling frequency
16 -0.8 2.4 12 -0.4 2.5 20 0 2.6 28 15 D-0.5 D D+0.5
bits dBfs V k nV ----------Hz dB Fref=138KHz, PGA gain=0dB, Vin = 0dBr (2.4Vpd) Measured on each single input Between RXN and RXP @gain=+31dB, frequency>138KHz Receive Programmable gain. D is the binary value of the control word. (see Section 4.7.1.1 - Rx Gain Control on page 10
c
Step size Attenuator 0 >= Att >= -3 d Step size 4dB Att step size AAF cutoff frequency Output SDR 2 tones
e
0.8 4*Att-0.5
1 4*Att
1.2 4*Att+0.5
dB dB Receive attenuator ATT is the binary value of the control word. (see Section 4.7.1.1 - Rx Gain Control on page 10
3.5 1 66
4 1.4
4.5 2
dB MHz dBc -3dB corner vs low frequency For RxPGA gain=31dB, measured at output of ADC.
Notes: a. The corresponding typical value correspond to a 2.4Vpd at RXN/RXP differentiel inputs. The 2.4Vpd correspond to what will be called 0dBr for the other specifications in the present table. Variations include process, temperature and power variations. b. The input noise must be measured in the frequency domain from 138KHz to 1.1MHz, with an sinusoidal input signal at -60dBr amplitude. Frequency of the input signal is 552KHz. c. D is the gain relatively to the 0dBr previously defined. Variations include process, temperature and power variations. d. Monotonicity is guaranted for RxPGA, Attenuator, but separatly. e. Ratio between max peak amplitude of one of the 2 single tones to any spurious measured in the down-stream band [138KHz-1.1MHz] ; each tone amplitude is at -6-31=-37dBr. The couples are (f1,f2) = (200KHz, 300KHz), (400KHz, 500KHz), (600KHz, 700KHz).
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5.4 - Transmit Path Specifications TA = 0 to 70C unless otherwise specified. The following specifications are guaranteed only when the Digital Control Interface is not active. Table 10 : Transmit Path Specifications
Typical specifications apply for VCC = 5.0V, temperature = 27C, nominal process and bias current. Maximum and minimum performance is with VCC 5%, 0C < Tambient < 70C, and worst case process and bias current. Description Input word rate Input word resolution PGAP/PGAN OUTPUT Common mode voltage Load resistance Load capacitance Output Impedance Reference Output signal Output noise Cutoff frequency Gain,0 D 15 step size 1dB Step size TXP/TXN OUTPUT Common mode voltage Load resistance Load capacitance Output Impedance Output SDR 2 tones ADSL/POTS 2 tones ADSL/ISDN
c d b a
Min.
Typ. 8.832
Max.
Unit MHz
Comments
16
bits
2.4 500
2.5
2.6
V
Measured on each output Single ended Single ended Single ended Differential output @0dB gain for TxPGA See also mask diagram below ("Final PGAP/N noise mask") @-3dB Programmable attenuator.
10 1 -5% 2.4 5 +5% 45 4 -D-0.5 0.8 -D 1 -D+0.5 1.2
pF Vp nV ----------Hz MHz dB dB
2.4 500
2.5
2.6
V
Measured on each output Single ended Single ended Single ended For TxPGA gain = 0dB
10 1 79 71 5
pF dB
Notes: a. This will represents the 0dBr for the other specifications in the present table. The level is mesured for the frequency of 30KHz which will correspond to the reference frequency. Variations include process, temperature and power variations. b. This gain is given relatively to the 0dBr previously defined. Variations include process, temperature and power variations. c. Ratio between max peak amplitude of one of the 2 single tones to any spurious. Measure performed for a dual tone signal (each tone with an amplitude equal to -6dBr), in range 30KHz to 1MHz (couple (f1,f2) are (70KHz, 80KHz), (120KHz, 130KHz)). d. Ration between max peak amplitude of one of the 2 single tones to any spurious. Measure performed for a (250KHz, 260KHz) dual tone signal (each tone with an amplitude equal to -6dBr), in range 30KHz to 1MHz.
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ST70136
Figure 8 : Tone Detector Schematic
VDDA6
TOP (PAD)
ACTD (PAD)
G
VDDA6
TON (PAD)
All cells are supplied with VDD except ESD diodes
Table 11 : Tone DetectorSpecifications
Description Zin listening mode Zin normal mode Minimum differential input signal Maximum diffential input signal VCM input VDD/2 Minimum 3.5 350 15 VDD Typical 5 500 Maximum 6.5 650 Unit k k Vp Comments Diffferential Diffferential Peak to peak In listening mode In listening mode
5.5 - VCXO Unless otherwise noted, typical specifications apply for AVdd = 5.0V, DVdd = 3.3V, temperature = 27C. A voltage controlled crystal oscillator is integrated in ST70136. Its nominal frequency is 35.328MHz. The quartz crystal is connected between XTALI and XTALO pins. Figure 9 : DAC VCXO Schematic
IVCO (PAD)
PMOS
VCO<7:0> (from internal register)
DIGITAL
ANALOG
VCXOUT (PAD)
VCOCAP(PAD) VREF
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ST70136
TA = 0 to 70C unless otherwise specified. Table 12 : DAC 8B Specifications
Typical specifications apply for VCC = 5.0V, temperature = 27C, nominal process and bias current. Maximum and minimum performance is with VCC 5%, 0C < Tambient < 70C, and worst case process and bias current. Description Number of bit Sampling rate DNL INL max code (FFh) mid code (80h) min code (00h)
a a a a a
Minimum
Typical 8
Maximum
Unit
Comments
1 -0.5 -2 2.42 3.57 4.74 -10 -20 320 350 500 500 10 2.52 3.63 4.77 0.5 2 2.62 3.69 4.80 10 20 680 650
KHz LSB LSB V V V mV mV k F Iout variation from 10A to 400A, @ code max, VCXOUT = 2.4V
Offset IVCO vs VCOCAP b Offset variation with current VCOCAP Zout VCOCAP Zout VCOCAP load
c d
Notes: a. Measured at VCOCAP output, filter disabled. b. Filter disabled, current through IVCO = 10A, VCXOUT = 2V. c. Filter enabled. d. Filter disabled.
5.6 - Crystal Table 13 : Crystal Parameters
Parameter Start up time Clock Frequency Frequency adjustment range Symbol TSU CLKM XADJ -100 35.328 100 Minimum Typical Maximum 7 Unit ms MHz ppm
Note: Recommended Crystal: MELCOM 35.328MHz / UM1/ 30 / 30 / 0+70 / 15pF / FUND.
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ST70136
5.7 - Data and Control Timing Interface TA = 0 to 70C unless otherwise specified. Figure 10 : Data and Control Timing Interface
CLKM Tc CLKWD Tva RX[0:3]
Tc To
TX[0:3] Ts Th Ts Th
CTRLIN Tva CTRLOUT Ts R/NW Th
Symbol
Description Data valid time Data setup time Data hold time Word clock delay CLKM Frequency CLKM clock duty cycle
Minimum 0 13 2 0
Typical
Maximum 4
Unit ns ns ns
Tva Ts Th
Tc Fo
4 35.328
ns MHz
40 28.3
60
% ns
To
CLKM period
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ST70136
Figure 11 : Application Schematic ST70136
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ST70136
Figure 12 : CPE Application Synoptic
Rx path 7 th
TS636 3 rd Line Transfo&C 20 Khz 168 Khz R Hybrid 2 nd TS634 138 Khz
2 nd
1.3 Mhz
ST70136
1 st
ST70137
4 th
ADSL / POTS
138 Khz
138 Khz
Tx path
Rx path 7 th
TS636 5 th Line Transfo&C 110 Khz TS634 300 Khz R Hybrid 3 rd
2 nd
1.3 Mhz
ST70136
1 st
ST70137
4 th
ADSL / ISDN
Tx path
210 Khz
210 Khz
210 Khz
CPE Application synoptic
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ST70136
6 - PACKAGE MECHANICAL DATA Figure 13 : Package TQFP64 Full Plastic (10 x 10 x 1.40 mm)
A A2 64 e A1 49 0,10 mm .004 inch SEATING PLANE
1
48
16
33
E3 E1 E
17
D3 D1 D
32
L1
L
K
Millimeters Dimensions Minimum A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.45 0.05 1.35 0.17 0.09 12.00 10.00 7.50 0.50 12.00 10.00 7.50 0.60 1.00 0.75 0.018 1 1.40 0.22 Typical Maximum 1.60 0.15 1.45 0.27 0.20 0.002 0.053 0.007 0.004 Minimum
0,25 mm .010 inch GAGE PLANE
Inches (approx) Typical Maximum 0.063 0.006 0.055 0.009 0.057 0.011 0.008 0.472 0.394 0.295 0.0197 0.472 0.394 0.295 0.024 0.039 0 (Minimum), 7 (Maximum) 0.030
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B
c
ST70136
7 - PACKAGE MECHANICAL DATA Figure 14 : Package LFBGA64 (8 x 8 x 1.7 mm)
BALL 1 IDENTIFICATION A D1 f 8 A B C D E F G H b (64 PLACES) e A2 E1 E 7 6 5 4 3 2 1 f A1 D 0.15
Millimeters Dimensions Minimum A A1 A2 b D D1 e E E1 f 0.350 0.400 1.100 0.500 8.000 5.600 0.800 8.000 5.600 1.200 Typical Maximum 1.700 0.450 0.014 Minimum
Inches (approx) Typical Maximum 0.067 0.016 0.043 0.20 0.315 0.220 0.031 0.315 0.220 0.047 0.018
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ST70136
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2001 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States http://www.st.com
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